Consider a memory system that is composed of one cache and a main memory. The access to the main memory takes 28 ns. Given a clock frequency of 8 GHz, an instruction miss rate of 9%, and data instruction miss rate related to load and store instruction is 18%. Assume that the base CPI of 1 and that the percentage of instructions related to Store and Load is 22%. Calculate the delay caused by the cache in terms of the number of instructions). Answers are displayed to the nearest 2 decimal. Select one: O a. 29.03 O b. 60.48 O c. none of the options O d. 69.441 Consider a memory system that is composed of one cache and a main memory. The access to the main memory takes 12 ns. Given a clock frequency of 8 GHz, an instruction miss rate of 11%, and data instruction miss rate related to load and store instruction is 15%. Assume that the base CPI of 1 and that the percentage of instructions related to store and Load is 39%. Calculate the CPI for the system taking into consideration the delay caused by the memory system. Answers are displayed to the nearest 2 decimal. Select one: O a. 17.18 O b. 15.18 O c. none of the options O d. 16.18 Consider a computer system with 2 levels of caches L1 and L2. L1 Cache has l-Cache and a D-Cache. The I cache has a miss rate of 19.6% and the D-Cache has a miss rate of 12.3%. The miss penalty to L2 cache is 27 cycles. L2 cache miss rate is 73.9% and the miss penalty to the main memory is 111 cycles. The frequency of all data operations is 35.1%. Assuming a processor with no memory stalls has a CPI of 3. What is the CPI with memory stalls? Select one: O a. 29.08 Ob. 35.62 O c. 37.78