Consider a modulo 4 two-bit up-down counter with input I. I=1 causes the count to increment, e.g., 00->01->10->11, cycling back to 00 from state 11 (in other words, counting from 0 up to 3 repeatedly). I=0 causes the count to decrement, e.g., 11->10->01->00, cycling back to 11 from state 00. The output values (Q₁(t+1) and Q₀(t+1)) will always be the same as the next state (S₁(t+1) and S₀(t+1)) for this device.

The state transition diagram for this device is shown below:

1/01 00 01 0/00 1/00 0/11 0/01 1/10 0/10 11 10 1/11 Complete the state encoding table below using the same format as on the first row: Input: 1=0 11/11 Input: 1=1 01/01 Present state: 00 Present state: 01 Present state: 10 Present state: 11