Consider a pipelined processor that performs the five basic operations of Instruction Fetch,

Decode$/$Register Read, Execute, Memory and Register Write in more than five stages. To increase

throughput, the cache accesses are now pipelined, consisting of two stages, both for instruction and

data caches. Additionally, the pipeline organization consists of three execution units. First unit

consisting of one stage is for Integer Add$/$Sub$,$ Load$/$Store and Branch operations $($excluding

Multiply$/$Divide$).$ Second unit is for floating point $($FP$)$ Add$/$Sub operations, comprising two

stages. The third unit is dedicated for Integer and FP Multiply$/$Divide operations, comprising four

non$-$pipelined stages i$.$e$.$ no new operation can start until the previous is complete.

Consider the clock cycle time for the above pipeline to be $150ps$

a$)$ What is the latency of a Floating Point SUB instruction?

b$)$ Assuming there are no FP and integer multiply$/$divide instructions in a program, what is

the speedup achieved by pipelining the cache accesses and execution unit if compared

with the simple five$-$stage MIPS pipeline? Assume a rational clock cycle time for the five$-$

stage pipelined organization for answering this question.

c$)$ For a program, assume $25\%$ of the code consist of multiply instruction followed

immediately by another independent multiply instruction. What is the addition to the CPI

due to these instructions? What type of hazard would this be$?$

d$)$ Would the CPI as determined in part $($c$)$ increase if the consecutive multiply instructions

were dependent?