Consider a processor with 1GB (i.e., 230 bytes) of physical memory, a 32GB (i.e., 235 bytes) virtual address space and size of 32KB (i.e., 215 bytes) pages. The processor has a 64KB direct-mapped level 1 cache with a line (block) size of 128B (i.e., 27 bytes) and a 2MB (i.e., 221 bytes) 4-way (i.e., 4 lines/set) setassociative L2 cache with a line size of 256B (i.e., 28 bytes). The machine is byte-addressable.

a) Show the breakdown of the virtual and physical address, i.e., the total number of bits in the address, and the size, name as well as location of the fields used to address pages and offsets within a page.

b) Show the breakdown of the physical address as interpreted by the level 1 cache and level 2 cache. Identify the size and location of the fields of the physical address that are used to address the cache. Make sure you identify the size of each field as well as the total size of the address.

c) How many entries are there in the page table?

Virtual Address Physical Address