Consider a program that can execute with CPI $=1$ if we could magically service every load instruction within $1-$cycle $($L$1$ cache hit$).$

Now in practice, $9\%$ of all load instructions suffer from an L$1$ cache miss, $6\%$ of all load instructions suffer from an L$2$ cache miss, and $3\%$ of all load instructions suffer from an L$3$ cache miss $($and are serviced by the memory system$).$

An L$1$ cache miss stalls the processor for $8$ cycles while the L$2$ is looked up$.$ An L$2$ cache miss stalls the processor for $25$ cycles while the L$3$ is looked up$.$ An L$3$ cache miss stalls the processor for $200$ cycles while data is fetched from memory. What is the CPI for this program if $35\%$ of the program's instructions are load instructions? $($Assume these delays add, i$.$e$.$ the worst case stalls for $8+25+200$ cycles.$)$