Consider a program that consists of four memory-access instructions and four arithmetic instructions. Assume that there are no data dependencies between the instructions. Two versions of this program are executed on the superscalar processor shown in Figure 6.13. The first version has the four memory-access instructions in sequence, followed by the four arithmetic instructions. The second version has the memory-access instructions interleaved with the arithmetic instructions. Draw two diagrams similar to Figure 6.14 to compare the execution of these two versions of the program Reference of Fig. 6.13,6.14. Fetch unit Instruction queue Arithmetic Dispatch unit Write results Load/Store unit Figure 6.13 A superscalar processor with two execution units