Consider a resistive load SRAM cell schematic shown below, which is also known as 4-T SRAM cell. Assume that that node Q is in state 0. In order to read the cell, both bit lines, BL and ~BL, are precharged to VDD. Determine the minimum (W/L)M1 so that the cell cannot erroneously flip when it is selected. Assume that the switching threshold VM of the resistive load inverter equals 0.6V (VM = Vin = Vout at this point for the resistive load inverter). Also, assume that VDD = 1.3V, RL = 50kΩ, VTN = 0.4V, and k’ n = 100μA/V2. Ignore the body effect