Desfin Speciffeations: Design a FSM that has one input bit stream X and one output $Z,$ with the following functionality:

On startup we look at detecting the seruence $000$ first and then $000$ again $($no overlapallowed$).$

After the leading sequence $(000)$ is detected twice $($not necessarily consecutively$),$ without overlap, we ignore subsequent instances of $000\text{'}$s and look to detect the sequence $111$ once.

After a sequence $111$ is detected once, we ignore subsequent instances of $111\text{'}$s and look again to detect the sequence $000$ twice. The process continues alternating between the detection of the $000$ sequence twice and then the $111$ sequence once.

The fimina trace shown below depicts a possible example, usina Moore, depicting some detections events in order to clarify the prescribed functionality for this FSM$.$

If possible, provide alternative design solutions stating any trade$-$offis among them.

Use lopistu to verify, and demonstrate to the instructor, that your design works as intended.

$\backslash$table$[[,,,1,,,,,,,,,,,,,,,,,,,,,,,T,,,,,,,,],[x,1,0,0,0,0,0,1,3,3,0,1,1,1,1,0,O,0,1,1,1,1,1,$a$.,$a$,0,0,0,0,$O$,1,1,1,,],[z,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,0,1,0,0,1,0,0,0,1,]]$

Design Constraints:

$($Wote: Every time you cannot meet one of the constraints you may lose a few points.$)$

Try not to use more than $4$ Flip$-$Flops of any type.

Iry to minimize the discreter gate count. State what you did in order to minimize the gate count.

The system can be a single FSM or use any number of subsystems for example one subsystem for each sequence to be detected$).$

You may use more Flip Flops, if needed, when providing altemative desien solutions, In such case discuss pros and cons.

Recall that no overlap is allowed when detecting $000$ twice.

You can use Moore or Mealy FEMs.

Bonus Work $($Gpts over final grade$)$: VHDL Implementation of your design

a$)$ Provide working VHDL code that is thoroughly commented and solve your design problem. Your code should follow the state diagram$/$diagrams that you originally develop to implement the sequence detector.

b$)$ Use Logisim to test$/$validate your VHDL design.

c$)$ To get credit provided detailed documentation of your code, demonstrate your work to the instructor and answer any questions regarding your code.

d$)$ Recall that your code should follow the state diagram$/$diagrams that you originally develop to implement the sequence detector. After this part you may try any other code that produces a working design.