Consider a sequential logic circuit consisting of three J K flip$-$flops $($with J $=$ K $=1)$ connected in cascade form. A $1$ KHz clock signal is applied to the first flip$-$flop FF$0.$ The Q output of FF$0$ is connected to the clock input of the second flip$-$flop FF$1,$ and Q$$ output of FF$1$ is applied to the clock input of the third flip$-$flop FF$2.$ Assume that all the flip$-$flops are negative edge triggered