Consider a simple 5-stage pipeline where each stage takes different times to complete: IF 5 ns, ID 1 ns, EX 4.5 ns, MEM 3 ns, and WB 2 ns. Assume that there is 1.5 ns delay associated with other design constraints (latches and clock skew). Furthermore, assume that we would like to execute only 50 instructions. Compute the clock period, speedup, efficiency, and throughput for this simple pipelined processor.

please, help.