Question: Consider a system with a five-level page table where each level in the page table is indexed by 9 bits and pages are 4 kB

Consider a system with a five-level page table where each level in the page table is indexed by 9 bits and pages are 4 kB in size. A TLB is provided that is indexed by the first 57 bits of the address provided by the process and achieves a 90% hit rate. The main memory access takes 40 ns while an access to the TLB takes 10 ns. The maximum memory read bandwidth is 100 GB/s.

i. What is the effective memory access latency?

ii. A colleague suggests replacing the system above with one that provides 80 GB/s memory read bandwidth and main memory access latency of 30 ns. Explain whether you should accept the replacement or not, and why.

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