Consider a system with a single level of cache with separate L$1$ data $($D$-$cache$)$ and L$1$ instruction $($I$-$cache$)$ caches. Assume that the D$-$cache hit rate is $93\%$ and the I$-$cache hit rate is $98\%.$ Further assume that the cache miss penalty is $100$ cycles, load$/$store instructions account for $30\%$ of all instructions and the baseline CPI $($assuming perfect caches$)$ is $1.$ This means that the L$1$ cache hits are already included in the baseline CPI.