Consider a timed process with two input events x and y and an output event z. Initially, the process is waiting to receive an input event x?. If this event occurs at time t, then the process waits to receive an input on the channel y. If the event y? occurs before time t + 2 or does not occur before time t + 5, then the process simply returns to the initial state, and if the event y? is received at some time t' between times t + 2 and t + 5, then the process issues an output event on z at some time between times t +1 and t+6 and returns to the initial state. Unexpected input events (e.g., the event y in the initial mode) are ignored. Design a timed state machine that exactly models this description. Consider a timed process with two input events x and y and an output event z. Initially, the process is waiting to receive an input event x?. If this event occurs at time t, then the process waits to receive an input on the channel y. If the event y? occurs before time t + 2 or does not occur before time t + 5, then the process simply returns to the initial state, and if the event y? is received at some time t' between times t + 2 and t + 5, then the process issues an output event on z at some time between times t +1 and t+6 and returns to the initial state. Unexpected input events (e.g., the event y in the initial mode) are ignored. Design a timed state machine that exactly models this description