Problem 2 (15%) Consider a timed process with an input event x and two output events y and z. Whenever the process receives an input event on the channel x, it issues output events on the channels y and z such that (1) the time delay between x? and y! is between 2 and 4 units of time, (2) the time delay between x? and z! is between 3 and 5 units of time. While the process is waiting to issue its outputs, any additional input events are ignored. Design a timed state machine that exactly models this description and draw a finite state machine of your design. Problem 2 (15%) Consider a timed process with an input event x and two output events y and z. Whenever the process receives an input event on the channel x, it issues output events on the channels y and z such that (1) the time delay between x? and y! is between 2 and 4 units of time, (2) the time delay between x? and z! is between 3 and 5 units of time. While the process is waiting to issue its outputs, any additional input events are ignored. Design a timed state machine that exactly models this description and draw a finite state machine of your design