Consider a virtual memory system using a 3-level page table where the parameters n and p are 48 and 17, respectively. The size of the DRAM is 4GB. The number of bits of virtual address used for indexing into the first- and the second-level page tables are 10 and 10, respectively. Suppose each page table entry in the outermost level is 8 bytes long. How much memory is required for the page tables translating the user portion of the address space when the process address space looks as follows: The code+data segment grows upwards starting from address Ox000000000000 and is of size 2 MB. The heap grows upwards from address Ox000005000000 and is of size 10 MB. The stack grows downwards from address OxCFFFFFFFFFFF and is of size 15 MB. Consider a virtual memory system using a 3-level page table where the parameters n and p are 48 and 17, respectively. The size of the DRAM is 4GB. The number of bits of virtual address used for indexing into the first- and the second-level page tables are 10 and 10, respectively. Suppose each page table entry in the outermost level is 8 bytes long. How much memory is required for the page tables translating the user portion of the address space when the process address space looks as follows: The code+data segment grows upwards starting from address Ox000000000000 and is of size 2 MB. The heap grows upwards from address Ox000005000000 and is of size 10 MB. The stack grows downwards from address OxCFFFFFFFFFFF and is of size 15 MB