Consider adding support for register-memory ALU operations to the classic five-stage pipeline. To offset this increase in complexity, all memory addressing will be restricted to register indirect (i.e. all addresses are simply a value held in a register; no offset or displacement may be added to the register value). For example, the register-memory instruction add x4, x5, (x1) means add the contents of register x5 to the memory location with address equal to the value in x1 and put the result in x4. Register-register ALU operations are unchanged. The following items apply to the integer pipeline.

a) List a rearranged order of the five traditional stages of the pipeline that will support register-memory operations implemented exclusively by register indirect addressing.

b) For the reordered stages of the pipeline, what new data hazards are created by this addressing mode? Give an instruction sequence illustrating each new hazard. Assume forwarding is used if possible.

c) Give an example of code using the original pipeline without register-memory instructions that has a different instruction count than equivalent code using the new register-memory instruction.

d) What process could you take to measure if the register-memory instruction will improve performance?