For problem $7$: assume that only sources can use the new addressing mode.

C$.6[\frac{12}{13}\frac{?}{?}\frac{13}{15}\frac{?}{15}]$ C$\mathrm{.}1,$ C$\mathrm{.}2,$ C$\mathrm{.}3>$ We will now add support for register$-$memory ALU operations to the classic five$-$stage RISC pipeline. To offset this increase in complexity, all memory addressing will be restricted to register indirect $($i$.$e$.,$ all addresses are simply a value held in a register; no offset or displacement may be added to the register value$).$ For example, the register$-$memory instruction ADD R$4,$ R$5,($R$1)$ means add the contents of register R$\mathrm{.}5$ to the contents of the memory location with address equal to the value in register $RI$ and put the sum in register R$4.$ Register$-$register ALU operations are unchanged. The following items apply to the integer RISC pipeline:

a$.[12]$ List a rearranged order of the five traditional stages of the RISC pipeline that will support register$-$memory operations implemented exclusively by register indirect addressing.

b For the reordered stages $of$ the RISC pipeline, what new data hazards are created $by$ this addressing mode? Give $an$ instruction sequence illustrating each new hazard.

List all $of$ the ways that the RISC pipeline with register$-$memory ALU operations can have a different instruction count for a given program than the original RISC pipeline. Give a pair $of$ specific instruction sequences, one for the original pipeline and one for the rearranged pipeline, $to$ illustrate each way.

$e.[15]$ Assume that all instructions take $1$ clock cycle per stage. List all $of$ the ways that the register$-$memory RISC can have a different CPI for a given program $as$ compared $to$ the original RISC pipeline.$[13]$ Describe what new forwarding paths are needed for the rearranged pipeline $by$ stating the source, destination, and information transferred $on$ each needed new path.

$c.[13]$ For the reordered stages $of$ the RISC pipeline, what new data hazards are created $by$ this addressing mode? Give $an$ instruction sequence illustrating each new hazard.

List all $of$ the ways that the RISC pipeline with register$-$memory ALU operations can have a different instruction count for a given program than the original RISC pipeline. Give a pair $of$ specific instruction sequences, one for the original pipeline and one for the rearranged pipeline, $to$ illustrate each way.

$e.[15]$ Assume that all instructions take $1$ clock cycle per stage. List all $of$ the ways that the register$-$memory RISC can have a different CPI for a given program $as$ compared $to$ the original RISC pipeline.