. Consider constructing a 2Gbyte memory module organized as 256M addresses with 8 byte words using as many of the 1Gbit DRAM integrated circuits of Problem 13 as necessary

What size address bus (how many address lines) is needed for the memory module?

What size data bus (how many data lines) is needed for the memory module?

How many of the 1Gbit DRAM integrated circuits would be required for the memory module?

How many integrated circuits are needed in a bank to create the 8 byte word size?

How many banks are needed for the memory module?

What size external decoder is needed to select one of the banks in the memory module?