Consider following cache configuration.

$-$ The processor has separate instruction and data cache whose size is $32$ KB each

$-$ The size of the block is $32$ bytes.

$-$ The miss penalty $($fetching a block from the memory or writing a block to the

memory$)$ is $100$ clock cycles.

$-$ A cache is a writeback cache.

$-$ At any given time, $50\%$ of blocks are dirty $($written$).$

$-$ Instruction cache miss rate is $5\%$

$-$ Data cache miss rate is $3\%.$

$-$ The percentage of load and store instructions is $20\%.$

$-$ No write buffer is used.

$($e$)[5$ points$]$ Compute the additional CPI stall cycles due to I cache misses.

$($f$)[5$ points$]$ Compute the additional CPI stall cycles due to D cache misses.