Consider having alternative circuit designs for ID and WB that slow them down from 100ps to...

 

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Consider having alternative circuit designs for ID and WB that slow them down from 100ps to 200ps. Meanwhile, other hardware steps - IF, EX, MEM - remain the same as in class (i.e., 200ps). In this problem, you will explore the impact on both the single-cycle design and pipeline; so both single-cycle design and pipeline will have the slower circuit designs for instruction decode and register writeback. Assume an idealized instruction sequence without any pipeline hazard. Compared to the pipeline speedup of 4 covered in class, does having slower circuits for ID and WB improve the speedup due to pipelining? Justify your answer by calculating the new steady-state pipeline speedup. Consider having alternative circuit designs for ID and WB that slow them down from 100ps to 200ps. Meanwhile, other hardware steps - IF, EX, MEM - remain the same as in class (i.e., 200ps). In this problem, you will explore the impact on both the single-cycle design and pipeline; so both single-cycle design and pipeline will have the slower circuit designs for instruction decode and register writeback. Assume an idealized instruction sequence without any pipeline hazard. Compared to the pipeline speedup of 4 covered in class, does having slower circuits for ID and WB improve the speedup due to pipelining? Justify your answer by calculating the new steady-state pipeline speedup.