Question: Consider Listning 1 on the last page. Assume the code is executed on a 32-bit MIPS processor that includes an instruction cache with the following

 Consider Listning 1 on the last page. Assume the code is

executed on a 32-bit MIPS processor that includes an instruction cache with

Consider Listning 1 on the last page. Assume the code is executed on a 32-bit MIPS processor that includes an instruction cache with the following properties: Capacity = 512 bytes, direct mapped, block size 8 bytes. Assume that the cache is empty (all valid bits are zero) before you call function sum. (a) Will the instruction cache utilize temporal locality or spatial locality, or both? (b) What is the instruct cache miss rate when executing the function? Only count the memory accesses within the function, that is, the first instruction in the function is xor and the last one jr. The function is called with the following C statement sum( 0x6ff 1000, 100) ; and the first instruction of sum is located at address 0x00400000. Answer as a rational number. Consider Listning 1 on the last page. Assume the code is executed on a 32-bit MIPS processor that includes an instruction cache with the following properties: Capacity = 512 bytes, direct mapped, block size 8 bytes. Assume that the cache is empty (all valid bits are zero) before you call function sum. (a) Will the instruction cache utilize temporal locality or spatial locality, or both? (b) What is the instruct cache miss rate when executing the function? Only count the memory accesses within the function, that is, the first instruction in the function is xor and the last one jr. The function is called with the following C statement sum( 0x6ff 1000, 100) ; and the first instruction of sum is located at address 0x00400000. Answer as a rational number

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