$5.$ Suppose we have a $32-$bit MIPS processor, which includes a $2-$way set associative data cache with capacity $16384$ bytes, $16$ bytes block, and a least recently used $($LRU$)$ replacement policy. Assume that the cache is empty $($all valid bits are $0)$ before the following code is executed.

$1$ lw $t$1,0$x$1040($$$0)$

$2$ lw $t$2,0$x$2044($$$0)$

$3$ lw $t$3,0$x$3048($$$0)$

$4$ lw $t$4,0$x$1044($$$0)$

$5$ lw $t$5,0$x$504$c$($$$0)$

$6$ lw $t$6,0$x$3040($$$0)$

For each of the six assembly instructions above, state i$)$ the set field value for the accessed address, ii$)$ the tag field value, and iii$)$ if the instruction results in a cache hit or a cache miss.