Consider the $3$ processors with different cache configurations

a$.$ Cache $1$: Direct$-$mapped with one$-$word blocks

b$.$ Cache $2$: direct$-$mapped with $4-$word blocks

c$.$ Cache $3$: Two$-$way set associative with $4-$word blocks

The following are the miss rates

a$.$ Instruction miss rate is $4\%$ and data miss rate is $6\%$

b$.$ Instruction miss rate is $2\%$ and data miss rate is $4\%$

c$.$ Instruction miss rate is $2\%$ and data miss rate is $3\%$

For the processors, one$-$half of the instructions contain a data reference. Assume

that the cache miss penalty is $6+$ Block size in words. The CPI for this workload was

measured on a processor with cache $1$ and was found to be $2\mathrm{.}0.$ Determine which

processor spends the most cycles on the cache miss.

$5.(20$ points$)$ If the cache access time determines the processor$$s clock cycle time,

which is often the case, AMAT may not correctly indicate whether one cache

organization is better than another. If the processor$$s clock cycle time must be

changed to match that of a cache, is this a good trade$-$off? Assume the processors

are identical except for the clock rate; assume $1\mathrm{.}5$ references per instruction and a

CPI without cache misses of $2.$ The miss penalty is $20$ cycles for both processors.

$($a$)$ What is the AMAT for the original machine with a $500$ MHz clock which takes a $1$

clock cycle for cache hit with a miss rate of $5\%?$

$($b$)$ What is the AMAT for the new machine that doubles the cache size to reduce the

miss rate to $3\%$ but causes the hit time to increase by $20\%?$

$($c$)$ What is the impact on the execution time if the new hit time is the clock cycle

time?