Consider two processors with different cache configurations:

Cache 1: Direct-mapped with one-word blocks

Cache 2: Two-way set associative with four-word blocks

The following miss rate measurements have been made:

Cache 1: Instruction miss rate is 3%; data miss rate is 6%

Cache 2: Instruction miss rate is 2%; data miss rate is 3%

For these processors, one-half of the instructions contain a data reference. Assume that the cache miss penalty is 6 + Block size in words.

Determine which processor spends more cycles on cache misses.