Consider the case of a processor with an instruction length of $14$ bits and with $16$ general$-$purpose

registers$$thus the size of the address$/$name fields is $4$ bits. $($I$.$e$.,$ we are saying that memory addresses are

specified indirectly here, via address registers.$)$ Given those parameters, can the ISA instruction set

support a set of $112$ instructions, $46$ of which are $0-$address$/$name instructions, $62$ of which are $1-$

address$/$name instructions, and $4$ of which are $2-$address$/$name instructions? Explain reasoning in full.