Problem $3.$ Consider the case of a processor with an instruction length of $12$ bits and with $32$ general purpose registers so the size of the address fields is $5$ bits.a$)$ Is it possible to encode $3$ two$-$address instructions, $30$ one$-$address instructions and $45$ zero address instructions in the instruction set?b$)$ Is it possible to encode $3$ two$-$address instructions, $31$ one$-$address instructions and $35$ zero address instructions.c$)$ Assuming the same instruction lengths and address field sizes and further assuming that there are already $3$ two$-$address and $24$ zero$-$address instructions. What is the maximum number of one$-$address instructions that can be encoded for this processor?