Consider the circuit in Fig. $12\mathrm{.}31$ from CMOS VLSI Design

book $(4$th Edition$)$ by Neil H$.$ E$.$ Weste and David Money Harris. Propose a set of transistor sizes for all the MOSFETs in the pre$-$charge, read, write circuitry and the sram cell itself. Make sure you have considered $$writeabilty$$ and $$read stability$.$ Estimate the delay to precharge a bit line assuming there are $512$ cells in the column. Assume diffusion capacitance of a MOSFET is equal to its gate capacitance. Assume $$n$/$p $=2.$ Estimate the time it takes to discharge a bit line to Vdd$/2.$ Express delays in multiples of a MOSFET$$s RC delay.

FIGURE $12\mathrm{.}31$ Complete pair of columns for two$-$way

multiplexed SRAM