Consider the following ARM assembly code mov r2, #10 L: ldr r3, [r0, #0] ldr r4, [r1, #0] mul r5, r3, r4 add r6, r6, r5 sub r2, r2, #1 add r0, r0, #4 add r1, r1, #4 cmp r2, #0 bgt L

a. Describe in plain English what does the code compute b. Compute the number of cycles needed for each loop iteration. Assume CPI is 1 for data processing, 5 for data transfer, and 2 for branching c. What is the average CPI for the above table d. Assume the clock cycle is 100ps, what is the total CPU time of running the above code. e. What type of locality does this code have for accessing the data in memory? Assume the difference between values in r0 and r1 is larger than 100, if the ldr instructions can load four adjacent words into the cache, what is the miss rate? Note that the cache has two sets, each set has a block of 4 words, with memory mapping as shown below, where the values are only placeholder to indicate the number of bits in each field. Tag Set Block Byteoffset [ 27 bits ] [0] [00] [00]