Consider the following ARMv8 instruction sequence:

LOOP: ldur X10, [X0,#0]

ldur X1, [X10,#0]

sub X2, X2, #1

cbnz X2, LOOP

add X0, X1, XZR

add SP, SP, #8

A) Assume the value in X2 was 2 before executing this code sequence. Now, assume that you have a 5-stage ARMv8 pipeline processor that supports full data forwarding and has a perfect branch predictor. The processor also uses a revised register file that accepts writes in the first half of a cycle and reads in the second half of a cycle. Please draw the pipeline diagram until the program reaches add SP, SP, #8.

B) With the processor in A, but assume the value in X2 was 10000 before executing this code sequence. How many cycles it takes for the program to reach add SP, SP, #8? Whats the average CPI?

C) Again, assume the value in X2 was 2 before executing this code sequence. Now, assume that you have a 7-stage MIPS pipeline processor which take 2 stages in both fetching instructions and data accesses. Therefore, the resulting pipeline processor will have the following stages IF1, IF2, ID, EX, MEM1, MEM2, and WB. If the processor supports full data forwarding and has a perfect branch predictor. The processor also uses a revised register file that accepts writes in the first half of a cycle and reads in the second half of a cycle. Please draw the pipeline diagram until the program reaches add SP, SP, #8