Consider the following code. Assume that initial values of all registers and memory are

zero.

Fill in the following table with a pipeline diagram, showing the execution of the DLX

code given above. Show the complete executions of all instructions up to and including

the second execution of the loop: SUBI R$4,$R$4,$#$1$ instruction. Use the following codes:

$F=$ fetch, $D=$ decode $x=$ execute, $M=$ memory access, $W=$ write back, $s=$ stall. List

the instructions corresponding to your pipeline diagram in the leftmost column. The

numbers above each column are provided to help you count cycles. Assume the

architecture shown on the next page the register block in a single cycle, resolves

the branch during decoding, and includes forwarding hardware$).$