Please solve all parts

In this exercise we compare the performance of $1-$issue and $2-$issue processors, taking into account program transformations that can

be made to optimize for $2-$issue execution. Problems in this exercise refer to the following loop $($written in C$)$:

for $(i=0$;$ij$;$i+=2)$

$b[i]=a[i]-a[i+1]$;

A compiler doing little or no optimization might produce the following MIPS assembly code:

addi $x12,x0,0$

jal ENT

TOP: slli $x5,x12,3$

add $x6,x10,x5$

lw $x7,0(x6)$

lw $x29,8(x6)$

sub $x30,x7,x29$

add $x31,x11,x5$

sw $x30,0(x31)$

addi $x12,x12,2$

ENT: bne $x12,x13,$ TOP

The code above uses the following registers:

Assume the two$-$issue, statically scheduled processor for this exercise has the following properties:

One instruction must be a memory operation; the other must be an arithmetic$/$logic instruction or a branch.

The processor has all possible forwarding paths between stages $($including paths to the ID stage for branch resolution$).$

The processor has perfect branch prediction.

Two instruction may not issue together in a packet if one depends on the other.$)$

If a stall is necessary, both instructions in the issue packet must stall.

As you complete these exercises, notice how much effort goes into generating code that will produce a near$-$optimal speedup.

$($a$)$ Draw a pipeline diagram showing how RISC$-$V code given above executes on the two$-$issue processor. Assume that the loop exits

after two iterations.

$($b$)$ What is the speedup of going from a one$-$issue to a two$-$issue processor? $($Assume the loop runs thousands of iterations.$)$

$($c$)$ Rearrange$/$rewrite the RISC$-$V code given above to achieve better performance on the one$-$issue processor. Hint: Use the

instruction "beqz $$s1,$ Done" to skip the loop entirely if $j=0.$

$($d$)$ Rearrange$/$rewrite the RISC$-$V code given above to achieve better performance on the two$-$issue processor. $($Do not unroll the

loop, however.$)$

$($e$)$ Repeat Exercise $4\mathrm{.}31\mathrm{.}1,$ but this time use your optimized code from Exercise $4\mathrm{.}31\mathrm{.}4.$

$($f$)$ What is the speedup of going from a one$-$issue processor to a two$-$issue processor when running the optimized code from

Exercises $4\mathrm{.}31\mathrm{.}3$ and $4\mathrm{.}31\mathrm{.}4.$

$($g$)$ Unroll the RISC$-$V code from Exercise $4\mathrm{.}31\mathrm{.}3$ so that each iteration of the unrolled loop handles two iterations of the original loop.

Then, rearrange$/$rewrite your unrolled code to achieve better performance on the one$-$issue processor. You may assume that $j$ is a

multiple of $4.$

$($h$)$ Unroll the RISC$-$V code from Exercise $4\mathrm{.}31\mathrm{.}4$ so that each iteration of the unrolled loop handles two iterations of the original loop.

Then, rearrange$/$rewrite your unrolled code to achieve better performance on the two$-$issue processor. You may assume that $j$ is a

multiple of $4.($Hint: Re$-$organize the loop so that some calculations appear both outside the loop and at the end of the loop. You

may assume that the values in temporary registers are not needed after the loop.$)$

$($i$)$ What is the speedup of going from a one$-$issue processor to a two$-$issue processor when running the unrolled, optimized code

from Exercises $4\mathrm{.}31\mathrm{.}7$ and $4\mathrm{.}31\mathrm{.}8?$

$($j$)$ Repeat Exercises $4\mathrm{.}31\mathrm{.}8$ and $4\mathrm{.}31\mathrm{.}9,$ but this time assume the two$-$issue processor can run two arithmetic$/$logic instructions

together. $($In other words, the first instruction in a packet can be any type of instruction, but the second must be an arithmetic or

logic instruction. Two memory operations cannot be scheduled at the same time.$)$