Question: Consider the following code describing a combinational logic:module DUT ( A , B , C , S , out ) ;input A , B ,

Consider the following code describing a combinational logic:module DUT (A, B, C, S, out);input A, B, C;input [2:0] S;output reg out;always @(*)beginif (S[0])out = A;else if (S[1])out = B;else if (S[2])out = C;endendmodulea. Draw the synthesized circuit out of the above code. What is the possible problemwith this design?b. Proposed two solutions to resolve this problem along with their synthesized circuits.

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