Please explain in details:

$1-$ Consider the following code describing a combinational logic:

module DUT $($A$,$ B$,$ C$,$ S$,$ out$)$;

input A$,$ B$,$ C;

input $[2$:$0]$ S;

output reg out;

always @$(*)$

begin

if $($S$[0])$

out $=$ A;

else if $($S$[1])$

out $=$ B;

else if $($S$[2])$

out $=$ C;

end

endmodule

a$)$ Draw the synthesized circuit out of the above code. What is the possible problem with this design?

b$)$ Proposed two solutions to resolve this problem along with their synthesized circuits.

c$)$ Implement the modified design in part $($b$)$ using tri$-$state buffers without using multiplexers. Show your architecture and RTL code.