Consider the following code segment on the 5-stage Pipelined MIPS architecture we discussed in class:

Loop: lw $t0, 0($s1) addu $t0, $t0, $s2 sw $t0, 0($s1) addi $s1, $s1, -4 bne $s1, $zero, Loop

Fill the pipeline schedule below for one iteration of the loop. Mark all hazards (e.g. you may use arrows). Assume forwarding between the pipeline stages is used whenever possible. Mark all data forwards. Also assume that the static "branch not taken" prediction strategy is used and that there is a 1 cycle penalty for branch misspredictions. Assume the loop is executed 10 times.

What is the average number of clock cycles for each iteration of the loop? What is the total execution time?

During the fifth clock cycle of the first iteration, which registers are being read and which registers will be written?

To minimize the wasted cycles due to hazards, unroll the loop two times assuming $s1 is a multiple of 8 and reorder the resulting code in order to minimize the stalls. You may use additional $t- registers as needed. Show how the new code is scheduled on the pipeline indicating any stalls and forwards. How many clock cycles are spent on an iteration of the loop on average now?

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