Question: Consider the following instruction sequence for a 5 - stage pipelined MIPS implementation 1 1 : addi $ s 1 , $ s 0 ,
Consider the following instruction sequence for a stage pipelined MIPS implementation
: addi $$
: Iw $s$s
: add $s $s $s
: add $$$
: add $s $s $s
Assuming that the initial values of $$$$ and $ are and respectively, and that memory locations and co
values and respectively.
Now consider the hazards and assume there is only ALUALU forwarding
What will be the final value of $
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