Consider the following loop.

Consider the following loop.

load.d r1, 0(r2)

addi r1, r1, #1

store r1, 0(r2)

addi r2, r2, #4

subi r4, r3, r2

bnez r4, Loop

Assume that the initial value of r3 is r2+596. Throughout this question, use the classic RISC five-stage integer pipeline and assume all memory accesses take 1 clock cycle.

a) Show the timing of this instruction sequence for the RISC pipeline without any forwarding or bypassing hardware but assuming a register read and a write in the same clock cycle forwards through the register. Assume branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cycles does the loop take to execute?

b) a) Show the timing of this instruction sequence for the RISC pipeline with normal forwarding or bypassing hardware but assuming a register read and a write in the same clock cycle forwards through the register. Assume branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cycles does the loop take to execute?

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