Consider the following MIPS assembly code:

LD R1, 45(R2)

ADD R7, R1, R5

SUB R8, R1, R6

OR R9, R5, R1

BNEZ R7, target

ADD R10, R8, R5

XOR R2, R3, R4

a) Identify each type of data dependency; list the two instructions involved; identify which instruction is dependent; and, if there is one, name the storage location involved.

b) Use MIPS five-stage pipeline (fetch, decode, register, execute, write-back) and assume a register file that writes in the first half of the clock cycle and reads in the second half cycle. Which of the dependencies that you found in part (a) become hazards and which do not? Why