Consider the following MIPS code:

(also assume, as with the assignment, variable timing CPU cycles rather than fixed time)

add $s0, $t0, $t1

sub $t2, $s0, $t3

beq $t2, $s3, LBL #assume they arent equal

add $s4, $t2, 1

done # as in our done macro, you don't need to do anything with this line

LBL: 

 mul $s4, $t2, 2 done #as in our done macro, you don't need to do anything with this line

Where instructions have the following pipeline stage times.

	IF	ID	EX	MEM	WB
Case 1	20	15	20	20	15
Case 2	25	5	30	10	20

1. Ignoring any hazards (and assume no speculative execution or branch prediction), what is the execution time in both cases.
2. Accounting for hazards (shared data and instruction cache) and assuming branches resolve in the mem stage what is the execution time in both cases