Consider the following state table:

Present State Input Next State Flip-flop inputs

A B x A B JA KA JB KB

0 0 0 0 1

0 0 1 1 0

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 1

1 1 1 0 0

a) Fill in the table to clearly indicate the J and K inputs to flip-flops representing states A and B.

b) Using Karnaugh maps as needed, determine minimal SOP expression for each JK flip-flop input.

c) Draw the complete circuit design using JK flip-flops and appropriate combinational logic.