Consider the following two VHDL code fragments:

PROCESS

BEGIN

WAIT UNTIL $($Clock$\text{'}$EVENT AND Clock$=\text{'}1\text{'})$;

IF reset$=\text{'}1\text{'}$ THEN

Q;

ELSE

Q D;

END IF;

END PROCESS;

PROCESS BEGIN

WAIT UNTIL $($Clock$\text{'}$EVENT AND Clock$=\text{'}1)$; reset$=\text{'}1,$ THEN Q;How do these two code fragments differ? Be specific. $(15$ points$)$