Question: Consider the following Verilog code for a T flip - flop. What is the correct code for the missing part? module t flip _ flop

Consider the following Verilog code for a T flip-flop. What is the correct code for the
missing part?
module t flip_flop (
input wire clk,d
input wire reset,
input wire
output reg q
always @(posedge clk or posedge reset)
if (reset) a
q <=1'b0;
else
// Missing code here
endmodule
O a. q <= t;
O b. None of the given options
O c. q <= t^q;
O d. q <=!q;
O e. The code is complete.

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