Consider the LEGv$8$ code below. Assume that $x1$ is initialized to $11$ and $x2$ is initialized to $22.$

ADDI $x1,x2,$ #$5$

ADDx$3,x1,x2$

ADDI $x4,x1,$#$15$

ADD$5,x1,x1$

$($a$)$ What would the final values of registers $x3$ and $x4$ be if the above instructions are executed in a pipeline processor that does not handle data hazards $($i$.$e$.,$ does not stall the pipeline or use data forwarding for data hazards$)?$

$($b$)$ What would the final values of register $x5$ be if the above instructions are executed in a pipeline processor that does not handle data hazards $($i$.$e$.,$ does not stall the pipeline or use data forwarding for data hazards$)?$ Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. See Section $4\mathrm{.}7$ and Figure $4\mathrm{.}51$ for details.

$($c$)$ Suppose you executed the code on a version of the pipeline from Section $4\mathrm{.}5$ that handles data hazards by simply stalling the pipeline $($i$.$e$.$ inserting NOP instructions where necessary$).$ Show the pipeline timing diagram below when the code is executed.

$\backslash$table$[[ADDIx1,x2,$#$5,$IF$,$ID$,$EX$,$MEM,WB$,,,,,,,,,,,,,,,],[ADDx3,x1,x2,,,,,,,,,,,,,,,,,,,,],[ADDIx4,x1,$#$15,,,,,,,,,,,,,,,,,,,,],[ADD55,x1,x1,,,,,,,,,,,,,,,,,,,,]]$

$($d$)$ Suppose you executed the code below on a pipeline from Section $4\mathrm{.}5$ that uses data forwarding for handling data hazards. Show the pipeline timing diagram below:

$\backslash$table$[[ADDIx1,x2,$#$5,$IF$,$ID$,$EX$,$MEM,WB$,,,,,,,,,,,,,],[ADDx3,x1,x2,,,,,,,,,,,,,,,,,,],[ADDIx4,x1,$#$15,,,,,,,,,,,,,,,,,,],[ADD5,x3,x2,,,,,,,,,,,,,,,,,,]]$