Consider the memory hierarchy using (a) one-word-wide memory organization,

(b) four-word-wide memory organization, and

(c) four memory-bank organizations. Assume that the cache block size is 4 words. The following memory access time is given:

- 1 clock cycles to send the address

- 16 clock cycles for each DRAM access initiated

- 1 clock cycle to send a word of data.

What are the miss penalties for each of these organizations?