Consider the MIPS instruction shown below: add $s0,$s1,$s2 This instruction is executed on two different machines: a pipelined machine ( 5 stages) and a non-pipelined machine. The following table shows the clock cycle time (CCT) for each machine: Which machine is faster and by how much? a. Equal performance. b. Non-pipelined by 2.78 times. c. Non-pipelined by 1.8 times. d. Pipelined by 1.8 times