1. Consider the operation of a machine with the data path of an ALU (Figure 2-2). Suppose that loading the ALU input registers takes 5 nsec, running the ALU takes 10 nsec, storing the result back in the register takes 5 nsec, and there is no pipeline. What is the maximum number of MIPS (Million Instructions per second) this machine is capable of (15%) ?

2. In a single-core CPU that has a five-stage pipeline, it takes 1 CPU clock cycle to fetch the instruction, 1 CPU clock cycle to decode the instruction, 1 CPU clock cycle to fetch the operands from the registers, 2 CPU clock cycles to execute the instruction, and 1 CPU clock cycles to write the result back to the register. How many CPU clock cycle does it need to execute approximately 60,000 instructions? You do not need to consider any storage other than the registers, and you should assume the instructions are executed in their original order (15%) .