Consider the program

add $1, $2, $3

sub $3, $4, $5

add $5, $6, $7

If we use the letters F, D, E, M and W to represent the fetch, decode, execute, memory, and writeback stages, a pipeline execution diagram for the executing sequence would be:

Now consider the following code executing on a processor design that supports delay slots (where the semantics of conditional branch instructions is different -- branches are delayed).

Draw a pipeline execution diagram for this code. Assume that when the code executes, conditions are evaluated such that branches are never taken.

1 2 3 4 5 6 78 F D E MW sub F D E MW add F D E M W