Consider the reservation table in Figure $2.$ Note that this is Figure $8\mathrm{.}4$ in the textbook. If you

are not familiar with it$,$ you should read Section $8\mathrm{.}2\mathrm{.}2$ Pipelining from the textbook. In this

question, we assume that the processor includes forwarding logic that is able to tell that in$-$

struction A is writing to the same register that instruction B is reading from, and that therefore

the result written by A can be forwarded directly to the ALU before the write is done. Assume

the forwarding logic itself takes no time. How many cycles are lost to the pipeline bubble