Consider two different implementations of the same instruction set architecture on two different

processors. The instructions can be divided into four classes according to their CPI $($class A$,$ B$,$

C$,$ D$).$ Processor P$1$ with a clock rate of $2$ GHz and CPIs of $1,2,3$ and $4,$ and Processor P$2$ with

a clock rate of $4$ GHz and CPIs of $3,3,3$ and $5$