Consider you are designing a processor around $64$ bytes cache, each block of

cache is $8$ bytes. Assume the memory address is $8$ bits. Assume you read$/$write $8$

bytes of block of data to$/$from the main memory per access.

a$)$ Identify how the address bits must be divided among block offset, cache

index and tag.

$(10$ points$)$

b$)$ Using suitable diagrams$/$tables representing the content of the cache, show

misses and hits when the following memory addresses are accessed in a

direct mapped cache. points$)$

OXe$0$

OXfO

$0$Xe$4$

$0$Xe$2$

$0xe0$

$0$Xe$8$

$0$Xf$4$

Using the provided addresses and corresponding tags, identify the cache

miss$/$hit$.$

c$)$ Using suitable diagrams$/$tables representing the content of the cache, show

misses and hits when the following memory addresses are accessed in a $2-$

way set$-$associative cache. Put cache block #$0,$ #$1$ in set #$0,$ cache block #$2,$

#$3$ in set #$1$ and so on$.$ State advantage$/$drawbacks of this design.

points$).$

OXe$0$

OXfO

$0$Xe$4$

$0$Xe$2$

$0xe0$

$0$Xe$8$

$0$Xf$4$

d$)$ Repeat $5($c$)$ using a fully associative cache. State advantage$/$drawbacks of

this design.

points$)$

e$)$ Repeat $5($a$)$ and $5($b$)$ using a cache block size of $16$ bytes, instead of $8$ bytes.

Assume you can read$/$write $16$ bytes at once from the main memory. State

advantage$/$drawbacks of this design. points$)$