Question: Considering a multicycle divider, divide 1 3 by 5 , indicating the values of the registers listed in the questions at the end of each

Considering a multicycle divider, divide 13 by 5, indicating the values of the registers listed in the questions at the end of each clock cycle indicated. Consider that the inputs and results are represented with 4 bits, and that at the end of cycle 0(initialization):
Quotient, Cycle 1
Remainder, Cycle 1
Divider, Cycle 1
Quotient, Cycle 2
Remainder, Cycle 2
Divider, Cycle 2
Quotient, Cycle 3
Remainder, Cycle 3
Divider, Cycle 3
Quotient, Cycle 4
Remainder, Cycle 4
Divider, Cycle 4
Quotient, Cycle 5
Remainder, Cycle 5
Divider, Cycle 5

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